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| author | Adam Carpenter <gitlab@53hor.net> | 2019-07-09 15:14:04 -0400 |
|---|---|---|
| committer | Adam Carpenter <gitlab@53hor.net> | 2019-07-09 15:14:04 -0400 |
| commit | 7e8ee5ed9cad6484e9f13f81731b102ced58402e (patch) | |
| tree | 5395402ab07bbb5a659dbd68c701e22a1227202f /meap/meap-code/ch5/ch5-cpu1 | |
| download | learning-rust-7e8ee5ed9cad6484e9f13f81731b102ced58402e.tar.xz learning-rust-7e8ee5ed9cad6484e9f13f81731b102ced58402e.zip | |
Init.
Diffstat (limited to 'meap/meap-code/ch5/ch5-cpu1')
| -rwxr-xr-x | meap/meap-code/ch5/ch5-cpu1/Cargo.lock | 4 | ||||
| -rwxr-xr-x | meap/meap-code/ch5/ch5-cpu1/Cargo.toml | 6 | ||||
| -rwxr-xr-x | meap/meap-code/ch5/ch5-cpu1/src/main.rs | 60 |
3 files changed, 70 insertions, 0 deletions
diff --git a/meap/meap-code/ch5/ch5-cpu1/Cargo.lock b/meap/meap-code/ch5/ch5-cpu1/Cargo.lock new file mode 100755 index 0000000..2baaa64 --- /dev/null +++ b/meap/meap-code/ch5/ch5-cpu1/Cargo.lock @@ -0,0 +1,4 @@ +[[package]]
+name = "ch5-cpu1"
+version = "0.1.0"
+
diff --git a/meap/meap-code/ch5/ch5-cpu1/Cargo.toml b/meap/meap-code/ch5/ch5-cpu1/Cargo.toml new file mode 100755 index 0000000..060a235 --- /dev/null +++ b/meap/meap-code/ch5/ch5-cpu1/Cargo.toml @@ -0,0 +1,6 @@ +[package]
+name = "ch5-cpu1"
+version = "0.1.0"
+authors = ["Tim McNamara <code@timmcnamara.co.nz>"]
+
+[dependencies]
diff --git a/meap/meap-code/ch5/ch5-cpu1/src/main.rs b/meap/meap-code/ch5/ch5-cpu1/src/main.rs new file mode 100755 index 0000000..c934c13 --- /dev/null +++ b/meap/meap-code/ch5/ch5-cpu1/src/main.rs @@ -0,0 +1,60 @@ +const ARITHMETIC_AND_LOGIC: u8 = 0x8;
+const HALT: u8 = 0x0; // <1>
+const ADD_XY: u8 = 0x4;
+
+struct CPU {
+ // current_operation: u16, // <2>
+ registers: [u8; 16], // <3>
+ position_in_memory: usize, // <4>
+ memory: [u8; 4096], // <5>
+}
+
+impl CPU {
+ fn run(&mut self) {
+ loop {
+ let op_byte1 = self.memory[self.position_in_memory] as u16; // <6>
+ let op_byte2 = self.memory[self.position_in_memory + 1] as u16; // <6>
+ let raw_op = op_byte1 << 8 | op_byte2; // <7>
+
+ let op_major = ((raw_op & 0xF000) >> 12) as u8;
+ let x = ((raw_op & 0x0F00) >> 8) as u8;
+ let y = ((raw_op & 0x00F0) >> 4) as u8;
+ let op_minor = (raw_op & 0x000F) as u8;
+
+ self.position_in_memory += 2; // <8>
+
+ match (op_major, op_minor) {
+ (HALT, HALT) => { return; }, // <9>
+ (ARITHMETIC_AND_LOGIC, ADD_XY) => self.add_xy(x, y),
+ _ => unimplemented!("opcode {:04x}", raw_op), // <10>
+ }
+ }
+ }
+
+ fn add_xy(&mut self, x: u8, y: u8) {
+ self.registers[x as usize] += self.registers[y as usize];
+ }
+}
+
+fn main() {
+ let mut cpu = CPU {
+ registers: [0; 16],
+ memory: [0; 4096],
+ position_in_memory: 0,
+ };
+
+ cpu.registers[0] = 5;
+ cpu.registers[1] = 10;
+ cpu.registers[2] = 10; // <11>
+ cpu.registers[3] = 10; // <11>
+
+ cpu.memory[0] = 0x80; cpu.memory[1] = 0x14; // <12>
+ cpu.memory[2] = 0x80; cpu.memory[3] = 0x24; // <13>
+ cpu.memory[4] = 0x80; cpu.memory[5] = 0x34; // <14>
+
+ cpu.run();
+
+ assert_eq!(cpu.registers[0], 35);
+
+ println!("5 + 10 + 10 + 10 = {}", cpu.registers[0]);
+}
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